june 1996 application note 44 designing fast ethernet and fddi-utp transceivers 1 overview the ML6673 is a complete monolithic transceiver for 125 mbaud mlt-3 (multi level threshold, 3 levels) encoded data transmission. the significance of this chip becomes evident when you consider todays requirement for wide-bandwidth transmission between computers and workstations. these computers, which may transmit applications involving color graphics, need high performance but a lower cost connectivity solution. the use of utp (unshielded twisted pair) reduces the cost of fast ethernet and fddi networks by replacing expensive fiber optic cable and components with low cost copper wiring. the key technical challenges in transmitting high speed data are controlling the emission and overcoming the bandwidth limitation of utp. therefore, in order to transmit data over utp, the ansi committee developed the x3t9.5 tp-pmd (twisted pair physical medium dependent) standard for twisted pair wiring. this standard allows the use of utp category 5 and stp (shielded twisted pair) cables. the tp-pmd standard applies to fddi transmission over twisted pair. the tp-pmd standard was later adopted by the fast ethernet 100base-tx standard, ieee 802.3. to achieve the high transfer rates three tasks must be performed: scrambling/descrambling, encoding/decoding and equalization. the latter two are performed by the ML6673. the first requirement is a two level nrzi scrambling of the transmitted data. once the data is scrambled to a two level nrzi and input to the chip, it gets converted to a multilevel threshold using the mlt-3. after the data has made its journey through the twisted pair, the receiver uses adaptive equalization to compensate for phase distortion and level attenuation. the data is subsequently converted back to nrzi format and descrambled. this application note will define these terms and standards and explain the benefits of each in achieving a low cost, high performance copper twisted pair network. mlt-3 line code the mlt-3 code is used for fast ethernet and fddi networks using copper media. mlt-3 is very similar to the nrzi (non return to zero, inverted) code used in the existing fiber fddi network. nrzi, is a two level unipolar code (0 and v) representing a one by a transition between two levels and a zero is represented by no transition as shown in figure 1. mlt-3 is a three level bipolar code (+v, 0 and Cv) representing a one by a transition between two levels and zero as no transition as shown in figure 1. hence, the maximum fundamental frequency of the mlt-3 is one-half that of nrzi. figure 2 shows the power spectral density for mlt-3 and nrzi. essentially, the use of the mlt-3 line code shifts much of the spectral energy to below 30mhz (as compared to nrzi). with the mlt-3 coding scheme, 90% of the spectral energy is below 40mhz versus 70mhz for nrzi, which achieves the same data rate but does not require a wideband transmission medium. 1
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4b/5b encoded,
scrambled dots
nrzi
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figure 1. nrzi and mlt-3 waveforms
2 application note 44 equalization during transmission of data over utp distortion and isi (intersymbol interference) are caused by dispersion in the cable. to overcome this signal corruption and distortion, the transmitted signal must be reconstructed from the incoming signal at the receiver. equalization is used to overcome this signal corruption. however, the distortion is frequency dependent and loop length dependent. since in most practical cases, the tp port characteristic is unknown and it is impractical to tune the equalizer specifically to each individual port. hence, an adaptive equalizer is used in the tp-pmd standard to ensure proper compensation of the received signal. by using an adaptive equalizer, the receiver automatically compensates for different lengths of cable without over equalizing or under-equalizing the line. the ML6673 monitors the energy of the received signal to determine the cable length and adjust the equalizer accordingly. the input signal level is inversely proportional to the cable length. therefore, as the signal level decreases, the amount of equalization is increased to compensate for the line loss. tp-pmd the tp-pmd standard for fast ethernet and fddi networks is intended to be a physical replacement of the odl (optical data link) transceiver. it contains a scrambler/descrambler, a mlt-3 transceiver (ML6673) and a transformer-common mode choke module as shown in figure 3. nrzi coded data is sent to the tp-pmd and the tp-pmd transmits the 125mbit/s mlt-3 coded data to the media. at the receive side, the mlt-3 coded data is received and equalized and then is converted into nrzi coded data. scrambler/
descrambler
rj-45
*transformer
module
mlt 3
transceiver
(ML6673)
*contact belfuse or, valor, regarding transformer module bel phone: (201) 432-0463 valor phone: (619) 537-2619 figure 3. block diagram of the tp-pmd figure 2. power density spectra for nrzi and mlt-3 125 mhz
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scrambling/descrambling in general, the robustness of a digital transmission system often depends on the statistical nature of the digital sources. for example, long strings of 0s and 1s can cause loss of the sychronization since the receiver clock is derived from the received data. therefore, data must contain adequate transitions to assure that the timing recovery circuit will stay in sychronization. the fast ethernet and fddi protocols allow for some repetitive data patterns. these patterns create energy peaks in the power spectral density of the line signal. these peak discrete spectral components are not desirable and must be suppressed. the utilization of scrambling spreads these patterns and suppresses discrete spectral components by 20 to 25db. this is due to the effect of randomization of the data and averages out the signal over a period of time. thus, the peak energy is eliminated and emission improved. the ansi committee has chosen stream-cipher scrambling as the technique for the tp-pmd network. the stream- cipher scrambler encodes a plain text nrz bit stream by addition (modulo 2) of a key stream to produce a cipher text bit stream. it is implemented by adding an 11 bit linear feedback shift register (lfsr) whose input bit is the exclusive-or of its 11th and 9th previous bit, and which contains at least one non-zero bit. the shift register generates the key stream sequence which can be added to valid plain text streams with an average run length of approximately two consecutive zeros and a maximum run length of approximately 60 consecutive zeros.
3 application note 44 transmit function the ML6673 receives an nrzi code bit stream, which is at positive differential ecl (pecl) levels at the txin inputs. pecl level scrambled nrzi data is received by the ML6673 and then converted into mlt-3 line code. the current driven transmitter then sends the data to the transformer/common-mode choke module. since the output structure of the twisted pair drivers is current driven, it has the following advantages when driving the utp medium: ? the differential outputs are well matched for balanced signal transmission. balanced transmission is crucial for meeting tight regulations on signal shapes. ? current driven outputs produce lower common-mode voltages for a lower emi radiation. this can be a very significant issue in meeting fcc regulations. ? the output drive can be easily adjusted to compensate for losses in the transformer module. an external resistor between pin 17 and 18, rtset1 and rtset2, sets the output level. the value of the resistor across pins 17 and 18 is as follows: rtset i out = 64 1 25 . for fddi utp and fast ethernet applications, the ansi x3t9.5 standard specifies the transmit voltage amplitude to be 2v p-p or 1v 60mv. the utp connection requires a termination impedance of 100 w , each transmitter output is terminated by one 50 w (r l ) resistor to provide the 100 w termination impedance. therefore, i vp p r v ma out l = - == 22 50 40 () w the value of rtset is rtset ma k = = 64 1 25 40 2 . using a 2k resistor sets the transmit level to 2v p-p with 0db loss at the transformer module and zero meter cable. if the transformer module attenuates the transmit signal level, the value of rtset should be decreased to generate 2v p-p signal after the transformer. the transmitter may be disabled by the txoff pin when this pin is pulled low. then, the transmitters output goes to a high impedance state and shuts off transmit bias current. receive function the receive circuit of the ML6673 consists of an adaptive equalizer and mlt-3 to nrzi converter. the equalizer adjusts its gain and frequency response as a function of the received signal. the equalization level is based on the energy level of the received signal. as the signal level decreases, due to higher attenuation by a longer cable, the amount of equalization is increased. the equalizer is designed to operate over a distance of 0 to 100 meters of category 5 type cable. the ML6673 detects the mlt-3 coded signal from the transformer module signal and activates the sd output signal when the input is above a preset the voltage level. this preset voltage threshold level is 25% of the maximum equalization setting. after the signal is equalized, it is converted to nrzi. the ML6673 sends data out in nrzi form. link status function the ML6673 monitors the line integrity and detects linkage with the signal detect circuit. a differential output pair sd to the host indicates the status of the link. they are active when a data signal is presented with an amplitude exceeding a preset threshold. otherwise, the signal detect circuit drives sd+ low and sdC high indicating an invalid link. loopback function loopback is controlled through the lpbk pin coming from the phy chip. when this pin is low, loopback is enabled and signal detect is asserted. during loopback, the transmitted data from txin does not transmit to the txout . instead it is looped back to the receive data rxout by an internal mux. tp-pmd circuit figure 4 shows a complete schematic of tp-pmd circuit using ML6673 with an external transformer module. this tp-pmd transceiver is designed to replace an existing 1408u odl fddi transceiver. the external resistors and capacitors are chosen to meet the following conditions: ecl line terminations rxout and sd are emitter-followers generating positive ecl (pecl) levels when terminated by a pair of resistors. the resistors form a thevinin equivalent 50 w termination. the following two equations are used to calculate the values of these resistors: rz r r bo a b == = == = 2 6 2 6 50 130 16 130 16 81 .. .. ww w w the same concept applies to the txin outputs coming from the phy. rxout , sd and txin are not terminated in the tp-pmd schematic since they are terminated at the other end in the adapter cards and concentrator boards. media termination two 50 w resistors at tpout and tpin implement 100 w terminating impedance for utp when looking back through the filter-transformer module. the tpout must be terminated by a 50 w resistor to +5v.
4 application note 44 common mode the received signal coming from utp at tpin must be biased by the cmref pin as shown in the schematic. the transmitted signal from the tpout is biased to +5v through the center top of the transformer module. equalizer and link detect timings the resistor across rrset1 and rrset2 sets the time constants controlling the equalizers transfer function. a 5k, 1% resistor across these pins limits the cable length to 100 meters. figure 4. schematic of the tp-pmd using the ML6673 c7
c8
4.7 m f 8 7 4 2 38 9 11 nc 13 nc 17 12 19 18 txin+ txin sd+ sd rxout+ rxout txoff lpbk tgndd tgnda rgndd rrset1 rrset2 tp1 tp2 v cc tx 16 15 14 25 29 27 28 31 30 1 5k
r3 32 ML6673ch rvccd tvccd tvcca rvcca rtset1 rtset2 v cc rx 10 20 c1 26 c2 7 c4 65 2k
r4 21 22 rj45 tpout+ tpout tpin+ cmref tpin 23 7 24 6 v cc tx r5 50 r6 50 31 4 c6 0.1 m f 22 r7 50 r8 50 1 1 nc nc nc nc 6 + v cc tx v cc tx 9 td td sd rd rd + v cc rx 0558-5999-00
or pt4172 5 0558-5999-00
or pt4172 3 nc 3 2 4 3 2 7 6 5 7 nc 5 8 6 nc v cc rx 5 4.7 m f nc nc 50 50 50 50
5 application note 44 performance data the ML6673 can be evaluated in the ML6673eval board. the ML6673 evaluation board provides access to all receive and transmit signals and waveforms required to test and evaluate the ML6673. as shown in figures 5 to 10, the ML6673 meets the standards for fast ethernet and fddi. receive waveforms the ML6673 evaluation board operates with different cable lengths. figures 5 through 8 show the typical eye pattern of the nrzi signals at the rxout pin, which is recovered by the internal adaptive equalizer for different cable lengths. in all cases, the jitter is held below 2.0ns. also the ML6673 is capable of handling baseline wander generated by a different pattern. baseline wander is the term used to describe what happens to the dc reference for a signal when voltage offsets cause the threshold to change. this issue occurs when a signal is being transmitted by using ac coupling to the transmission media, which, in this case, is twisted pair copper wire. this offset is what is called baseline wander. the tp-pmd standard defines a good symbol frame known as a killer frame in annex a.2. the killer frame produces a near worst case baseline wander condition of approximately 750mv. figures 9 and 10 show the typical eye pattern of the recovered nrzi data at the rxout pin for 0 (zero) and 117 meter cable lengths. in both cases the jitter is held below 2ns. figure 6. mlt eye pattern from the ML6673 eval board (25 meters utp cable) figure 8. mlt-3 eye pattern from the ML6673 eval board (117 meters utp cable) figure 5. mlt eye pattern from the ML6673 eval board (0 meter utp cable) figure 7. mlt eye pattern from the ML6673 eval board (50 meters utp cable)
6 application note 44 transmit waveforms typical rise time and fall time for the transmitted output after the transformer is approxiamately 2 to 3ns, as shown in figure 11. duty cycle distortion (dcd) is measured at the 50% voltage points on the rise and fall transitions as shown in figure 12. the 50% points at four successive transitions of figure 11. rise and fall time of the output transmit signal from the ML6673 eval board. figure 12. duty cycle distortion of the transmitter. mlt-3 are used when the binary bit sequence is 01010101. the deviations of the 50% crossing points from a best fit to a time grid of 16ns spacing does not exceed 0.25ns. figure 9. recovered nrzi data (killer frame) at the rxout pin for 0 (zero) meter cable length. figure 10. recovered nrzi data (killer frame) at the rxout pin for 117 meters cable length.
7 application note 44 layout considerations to obtain optimum performance from the tp-pmd transceiver, careful attention must be given to the layout of the board. the routing of sensitive input traces relative to other components and traces must be considered in great detail. data lines must be of controlled impedance and properly terminated to minimize reflections that might degrade performance. power supply pins must be protected from noisy operating conditions by proper filtering. to achieve this, the following should be considered: ? use a two layer printed wiring board with a large ground plane. ? use enough decoupling capacitors on the receive, transmit, digital, and analog vcc pins of the ML6673 to clean up the noise. locate these capacitors as close as possible to the appropriate pins of the ML6673. ? the receiver pins, and the traces connected to them, should be shielded by placing a ground trace between the pins, the traces and any other high-level paths to minimize the coupling of unwanted noise into the receiver. if shielding is not possible, route the transmitter-input traces and other traces carrying high- level signals as far as possible from the receiver pins. ? when laying out the traces for the data lines (txd, rxout, sd), signal lines should be an overshoot, as well as to simplify timing considerations arising from the propagation delay of a signal conductor. ringing and overshoot are due to the intrinsic inductance and capacitance at the end of the line. intrinsic inductance and capacitance are reduced by shortening the lines. the same concept applies to the tpout and tpin high speed input and output signal lines. ? each ecl data line should be terminated at the end of the line. a bypass capacitor, 0.01 to 1 m f, must be provided on the voltage side of the resistor for each termination resistor. the termination helps to minimize the reflection due to mismatch. ? avoid controlled impedance interruption (i.e., 90 bends) on all high speed lines. pc traces should be treated as transmission lines with continuous ground plane or power plane beneath each line. ? all 50 w termination resistors at tpout and tpin should be placed as close as possible to the pins of the ML6673. ? use the same +5v to pull up the two 50 w resistors at the tpout and the center tap of the transformer. adding a decoupling capacitor at this point is recommended. ? to improve the emi performance, terminate the unused pins of the rj45. different termination methods are available such as: a) adding a 50 w resistor to ground on each unused pin of rj45. b) adding an rc network on each unused pin to build a low pass filter, filtering high frequency components (higher than 40mhz). ? all paired lines (differential pairs) should be of equal length, especially tpout traces. ? the resistors across rtset1 adn rtset2 should be 2k w , 1% and close to the pins. ? a copy of the ML6673eval kit gerber files is included on the 3.5" floppy disk as a reference.
8 application note 44 micro linear reserves the right to make changes to any product herein to improve reliability, function or design. micro linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. the circuits contained in this data sheet are offered as possible applications only. micro linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. the customer is urged to consult with appropriate legal counsel before deciding on a particular application. 6/10/96 printed in u.s.a. 2092 concourse drive san jose, ca 95131 tel: 408/433-5200 fax: 408/432-0295 ? micro linear 1995 is a registered trademark of micro linear corporation
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